The present invention relates to improvements in the performance of integrated circuit amplifiers. More particularly, the present invention relates to improvements in the level shifting stage of an amplifier.
In typical voltage amplifiers, several NPN common-emitter gain stages are usually cascaded to achieve a high voltage gain. In discrete amplifiers, large-value capacitors can be used to couple the ac signal from one gain stage to the next without affecting dc bias levels in the amplifier. However, in integrated amplifiers, large-value coupling capacitors are usually not available because they require too much chip area. Therefore, to ensure adequate low-frequency response, the gain stages in integrated amplifiers are typically dc coupled. However, the output dc level in an NPN common-emitter gain stage is higher than the input dc level. Therefore, in a cascade of such gain stages, the dc level builds up, and it is considerably higher at the output of the last stage than at the input of the first stage. The output dc level therefore approaches the positive power supply voltage, and this reduces the possible swing of the output voltage of the amplifier.
The dc level build-up can be avoided in circuits using complementary NPN and PNP gain stages, but this approach is usually avoided because monolithic PNP transistors have poor gain and frequency characteristics.
A better way of overcoming the dc level build-up is to interpose a level shifting stage between each gain stage pair. The purpose of such a level shifting stage is to move the dc level downwards, and at the same time to act as a unity gain buffer for the ac signal. To fulfill its role as a buffer, a level shifting stage is required to have a relatively high input impedance, and a relatively low output impedance.
Various circuits have been proposed for level shifting stages. A popular conventional level shifting circuit is that of the LM118 operational amplifier commercially available from National Semiconductor Corporation and other manufacturers, which uses a differential PNP transconductance stage driving a differential current mirror. This level shifting stage is placed between a differential input stage and a main gain stage. In such designs, the deleterious effects of the PNP transistors in the level shifting stage can be reduced by the use of feedforward compensation, as is done in the LM118.
In an amplifier circuit in which feedforward compensation is used to bypass a slow PNP level shifting stage, it is desirable at high frequencies to convert the differential input signal to a single-ended signal prior to the level shifting stage. This has been accomplished in the LM118, for example, using a shunt capacitor to eliminate one-half of the high frequency signal provided to the level shifting stage, and it extends the useful bandwidth of the operational amplifier. The shunt capacitor, however, can cause settling time problems.
Applicants have invented an improved way to provide a single-ended signal from a differential input stage to a subsequent level shifting stage (or other type of second stage) without a shunt capacitor. This is achieved by directly coupling only one side of the input stage to the level shifting stage, and by generating a reference signal for input to other side of the level shifting stage which tracks the non-signal dc component of the directly coupled signal. For a further discussion of that invention, see applicants' co-pending application Ser. No. 07/673,466 filed concurrently herewith, entitled "Precise Reference Voltage Generator For Feedforward Compensated Amplifiers."
The type of conventional level shifting stage used in the LM118 has the disadvantage that it reduces the upper limit of the common-mode input voltage range of the amplifier to a value significantly below the positive supply voltage. This is because, as explained more fully elsewhere herein, there are several constraints that require the input dc levels of the level shifting stage to be more than a volt below the positive supply voltage for the amplifier. This disadvantage is especially important in amplifiers designed to work with low supply voltages.
The LM118 type of level shifting circuit also has the disadvantage that the differential PNP transistors, combined with the current mirror, introduces a phase delay that erodes amplifier stability for a given bandwidth. In the LM118, although one-half of the high frequency signal going into the level shifting stage is eliminated by the shunt capacitor, the other half of the high frequency signal is fed into the level shifting stage at the same time that it is being fed forward around this stage. The high frequency signal going through the level shifting stage appears at the output of the level shifting stage significantly out of phase with the fed forward high frequency signal. A primary cause of the phase shift through the level shifting stage is the differential operation of the PNP transistors which requires the signal to go through the current mirror. This phase shift causes the signal going through the level shifting stage to interfere with the fed forward signal, creating the above-mentioned erosion in stability. Thus, a level shifting circuit that did not require the high frequency signal to pass through the current mirror would have relatively less phase delay, and would provide a preferable level shifting circuit for use in a feedforward compensated amplifier which is single-ended before the level shifting stage.
In two other known operational amplifier circuits, the LM101A and LM741 commercially available from the National Semiconductor Corporation and other manufacturers, level shifting and differential-to-single ended conversion is accomplished in the input stage. The input stage includes a differential pair of NPN input transistors emitter coupled respectively to a pair of level shifting PNP transistors, which in turn drive a current mirror circuit. The PNP transistors are commonly driven by a current source connected to the base of each PNP transistor. The current conducted by each PNP transistor is differential, such that a differential change in either input causes a change in the current conducted by each PNP transistor, as well as a change in the current conducted by each side of the current mirror. Disadvantageously, the differential operation of the PNP transistors and the current mirror cause significant phase delay in a high frequency signal, similar to the level shifting stage of the LM118.
In view of the foregoing, it would be desirable to provide a circuit for a level shifting stage which does not require its input voltages to be significantly lower than the positive power supply voltage, thereby avoiding the possibility that the level shifting stage would limit the common-mode input voltage range or low voltage operation of an amplifier circuit.
It would further be desirable to provide a level shifting stage which does not require a single-ended high frequency signal to pass through a current mirror, thereby avoiding excess phase delay in the level shifting stage.